1. Field of the Invention
The present invention relates to a multi-layer semiconductor device, more particularly, it relates to a multi-layer semiconductor device having a heat sink.
2. Description of the Related Art
To improve the integration density of an integrated circuit, consideration has been given to the use of a planar integration density and a packaging technique therefor. Particularly, to improve the integration density, a mutualization of patterns has been carried out.
However, these considerations are self-evidently limited from the viewpoint of miniaturization of the integrated circuit.
Under this background, the present inventor filed Japanese Patent Application No. 59-60943, wherein integrated circuit chips are stacked to produce a stacked chip type multi-layer semiconductor device. The height of this structure of the multi-layer semiconductor device is decreased, and thus the integrated density is improved.
In such a structure of the multi-layer semiconductor device, however, the exotherm per unit volume is increased, which results in overheating, and thus it is relatively easy for a power-transistor having a high electrical heat element to be formed in the structure.
Moreover, since a heat sink metal plate is provided between stacked IC chips, electrical interconnection between each IC chip using a bump is difficult.